High Performance Wideband MSAG Gain Block/Driver Amplifier MMICS Using MLP Technology

By Michael Ashman and Inder Bahl
Cobham

The multi-level plating (MLP) process has been used to develop a family of wideband, low noise, generic gain block and driver amplifier MMICs operating up to 20 GHz. MLP implementation provides significant performance improvements over standard MMIC processing techniques, especially with regards to bandwidth and gain. This article discusses salient features of the MLP process, including test data for multilayer microstrip lines, spiral inductors, 3 dB couplers and MLP-based MMIC amplifiers. The design approach and test data for several broadband MMICs, including a low noise amplifier, a single-bias gain block, and 0.25 W and 0.7 W driver amplifiers, are also described.

Wideband, low noise, generic gain block and driver amplifier MMICs have been developed using many different device technologies including MESFET, HBT and PHEMT. Among these, PHEMT-based MMIC technologies have achieved superior performance due to inherent device high frequency operation capability. In order to achieve superior performance similar to PHEMT technologies, multifunction self-aligned gate (MSAG)-based MMICs are implemented using a multi-level plating (MLP) process. MLP utilizes multiple low dielectric constant polyimide and thick metallization layers atop the base GaAs. Designing with MLP allows for lower loss transmission lines or matching networks,1–3 higher frequency operation and increased flexibility in the development of higher power components.

At the M/A-COM facility in Roanoke, VA, the MSAG MESFET process4–9 is being used to develop low cost, high volume, high performance and highly reliable multifunction monolithic ICs for commercial and military applications. Because of its versatility in integrating low noise, power and high speed largescale integration (LSI) functions on a single chip, the process has been named the multifunction self-aligned gate process. The MSAG process eliminates the need for a gate recess, the single most important yield and reproducibility-limiting step. As each device type, which may include EFET, DFET, Schottky diode/limiter, low noise FET, switching FET, power FET and n' implants, is optimized for its respective function, it requires an additional mask. The MSAG process is available as a standard foundry service to outside users.

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Reprinted with permission of Microwave Journal from the December 2004 issue.